1. Field of the Invention
This invention relates generally to random access memories (RAM) as used in digital computers, and more particularly to a new and improved circuit for a memory cell of an integrated circuit two-port RAM that may be simultaneously interrogated by either one or both of two "read" signals and which is particularly valuable for use in large integrated circuits because of its very high switching speeds, very low standby current consumption, and small physical size.
2. Description of the Prior Art
Random access memories have been extensively used in digital computing equipment for many years. During this period, the equipment has been greatly reduced in size and increased in speed, and the various components, such as memories, input-output circuits, processing circuitry, and the like, have likewise been improved to the point where a RAM, originally comprising only eight cells each occupying about sixty square mils, are now commercially available on a single small integrated circuit chip and comprise several thousand cells each occupying only about one square mil. More recently, speeds have been vastly increased by the use of the two-port RAM in which the memory may be simultaneously addressed from two separate sources and read out on two different digit lines. These multiport RAMS have generally been in the form of a 90 .times. 110 mil integrated circuit containing sixteen complete JK flip-flops together with the necessary multiplexing and demultiplexing circuitry. Although relatively small in capacity, these memories are very versatile and have proven to be valuable, for example, as high speed buffer storage between processors, in fast multiplication circuitry, etc. Even more recently there have been attempts at reducing the size of the individual flip-flops making up a cell to thereby increase the storage capacity of the RAM. For example, one such commercially available microprocessor incorporates a two-port RAM having sixty-four memory cells in a sixteen-word by four-bit matrix. Each of the cells includes a two-transistor flip-flop circuit and an additional four transistors, eight resistors and three diodes and requires a total of eight connections to circuitry exterior of the cell. Each cell in the matrix draws nearly about one and one-half milliamperes of standby current, requires an area of about eighty-five square mils, and because of its design and process has an access time of approximately twenty-five nanoseconds.